Integrated circuit memories typically have an architecture in which memory cells are arranged in array blocks, with the array blocks being organized into banks. Each memory cell is accessed by appropriate activation of bitlines and wordlines. FIG. 1 is a simplified block diagram illustrative of a group 10 of the layout of an exemplary integrated circuit memory. Group 10 includes array blocks 11.sub.0 -11.sub.N) with shared sense amplifier banks 12.sub.0 -12.sub.N+1 disposed between array blocks 11.sub.0 -11.sub.N. Group 10 also includes a row decoder 14, wordline driver blocks 15.sub.0 -15.sub.N corresponding to array blocks 11.sub.0 -11.sub.N, and sense timing and control circuits 17.sub.0 -17.sub.N+1 corresponding to sense amplifier banks 12.sub.0 -12.sub.N+1.
A brief summary of the operation of group 10 during a memory access operation is set forth below. The summary is not intended to completely describe the operation of the integrated circuit memory, which is generally well known in the art, but rather to illustrate one of the timing parameters that designers generally seek to optimize.
A "row" portion of the memory address is received by row decoder 14, which then activates the appropriate wordline driver of wordline driver blocks 15.sub.0 -15.sub.N corresponding to the address. Typically, decoded address signals are received by the wordline driver blocks, which are then triggered by a row enable signal RE. That is, in a given cycle, the addressed wordline is not activated until row enable signal RE is asserted. Generally, the mapping of the memory addresses to memory cells is defined so that, depending on the number of array blocks, the most significant bits select one of memory arrays 11.sub.0 -11.sub.N, and the lower order bits select one of the wordlines within the selected array block. Thus, only one of array blocks 11.sub.0 -11.sub.N is selected at a time, with only one wordline within the selected array block being activated.
At about the time that the wordline of the selected array block is being activated, a corresponding sense amplifier bank for the selected memory cell is also activated. As shown in FIG. 1, sense timing control circuits 17.sub.0 -17.sub.N+1 provide control signals to the sense amplifier banks 12.sub.0 -12.sub.N+1 in response to sense enable signals SE.sub.0 -SE.sub.N+1. The timing between the activation of the sense amplifier bank and the availability of data from the selected memory cell is important with regard to access time and data detection, as described below. FIG. 2 illustrates the relationship between row enable signal RE, the bitline data signal and the corresponding sense enable signal. As shown in FIG. 2, row enable signal RE is represented by a a waveform 20, the bitline data signal is represented by a waveform 22 and the sense enable signal is represented by a waveform 24. As indicated by an arrow 20.sub.1, in response to row enable signal RE being asserted, the appropriate wordline driver is activated, which allows the memory cells connected to the activated wordline to drive their corresponding bitlines to the stored data levels. The accessing of the memory cell results in charge sharing differential on the bit line, as indicated by an arrow 22.sub.1.
In addition, as indicated by an arrow 20.sub.2, assertion of row enable signal RE is also involved in the assertion of the appropriate sense enable signal (indicated herein as signal SE.sub.Z, with Z representing an integer between zero and N+1, inclusive). The assertion of the sense enable signal causes activation of the corresponding sense amplifier bank, which amplifies the bitline signal. If the timing of signal SE.sub.Z is such that the leading edge of signal SE.sub.Z is relatively early (as illustrated by leading edge 25), then the corresponding sense amplifier bank SA.sub.Z can be activated before the corresponding selected memory cell can fully develop the data onto the selected bitline. As a result, the data could be sensed incorrectly and result in data corruption.
On the other hand, if the timing of signal SE.sub.Z is such that the leading edge of signal SE.sub.Z is relatively late (as illustrated by leading edge 26), then the corresponding sense amplifier bank SA.sub.Z can be activated a relatively long time after the corresponding selected memory cell fully develops data onto the corresponding bitline. Although the data will most likely be sensed correctly, the unneeded delay undesirably increases the minimum access time of the memory device. Accordingly, it is desirable to design the timing of signal SE.sub.Z such that the leading edge of signal SE.sub.Z occurs so as to activate the corresponding sense amplifier SA.sub.Z as soon as the selected memory cell develops the data on the bitlines, thereby allowing accurate sensing of the data while minimizing the access time. This is illustrated by leading edge 27 in FIG. 2.
FIG. 3 is a simplified block diagram illustrative of a group 30 of an integrated circuit memory that uses delay blocks 34.sub.0 -34.sub.N+1 to help control the timing of the sense amplifier activation. For clarity, the same reference numbers are used between drawings to indicate elements having the same or similar structure or function. Also, the row decoder and wordline driver blocks are omitted from the figure for clarity. Delay blocks 34.sub.0 -34.sub.N+1 are connected to receive row enable signal RE. Each delay block is designed to approximate the timing of the wordline activation in its corresponding array blocks. Also, sense timing control circuit 17.sub.0 -17.sub.N+1 are connected to receive the output signals of delay blocks 34.sub.0 -34.sub.N+1, respectively. Otherwise, group 30 is similar to group 10 (FIG. 1) in architecture.
One problem with this scheme is that the timing can be relatively inaccurate. More specifically, due to the physical layout of sense amplifier banks 12.sub.0 -12.sub.N+1, the propagation delay of row enable signal RE to the each of delay blocks 34.sub.0 -34.sub.N+1 will be different. Delay blocks 34.sub.0 -34.sub.N+1 are typically implemented with a series of inverters and, thus, may not accurately track varying propagation delays due to process variations. For example, wordlines are commonly implemented using polysilicon, which may have resistances that can vary for different process runs. Because the propagation delay of the wordlines can account for a significant portion of the delay between assertion of row enable signal RE and availability of the corresponding data on the bitlines, the timing of when data signals are available on the bitlines can vary significantly.
A refinement of this scheme is to place a block of unused memory cells near array blocks 11.sub.0 -11.sub.N to serve as delay block 32. This scheme may use boundary memory cells (i.e., not used for storage) that may already be present. The delay of this version of delay block 32 would be provided by the wordlines in this block of unused memory cells. This approach still does not address the differences in propagation delay due to the physical layout of sense amplifier banks 12.sub.0 -12.sub.N+1 and the extra unused memory cells and, in addition, may undesirably use a significant amount of chip area.
FIG. 4 is a simplified block diagram illustrative of a group 40 of an integrated circuit memory that uses selectively activated wordline drivers 42.sub.0 -42.sub.N along with mock wordlines 44.sub.0 -44.sub.N to control the activation of sense amplifier banks 12.sub.0 -12.sub.N+1. In this example, mock wordlines 44.sub.0 -44.sub.N are local boundary wordlines located on the left side of array blocks 11.sub.0 -11.sub.N, respectively, and are essentially identical to the normal wordlines of these array blocks. In FIG. 4, mock wordline drivers 42.sub.0 -42.sub.N are shown for driving mock wordlines 44.sub.0 -44.sub.N, respectively. As will be appreciated by those skilled in the art of integrated circuit memories, wordline drivers 42.sub.0 -42.sub.N are part of wordline driver blocks 15.sub.0 -15.sub.N (FIG. 1), with the other wordline drivers for the normal wordlines being omitted for clarity.
In this scheme, when a sense timing control circuit 17.sub.Z (Z being an integer between zero and N, inclusive) is to be activated, the mock wordline in array block 11.sub.Z (i.e., the array block to the right of the sense amplifier bank to be activated in this example circuit) is used to propagate the activation signal. In this example, mock wordlines 44.sub.0 -44.sub.N are connected to corresponding wordline drivers 42.sub.0 -42.sub.N, respectively. Wordline drivers 42.sub.0 -42.sub.N are connected to the output leads of NAND gates 46.sub.0 -46.sub.N, which are all also connected to receive row enable signal RE as an input signal. In addition, in this example, NAND gates 46.sub.0 -46.sub.N-1 are connected to receive enable signals SE.sub.0 -SE.sub.N-1, respectively, as another input signal. NAND gate 46.sub.N is connected to receive the logical OR of sense enable signals SE.sub.N and SE.sub.N+1. Mock wordlines 44.sub.0 -44.sub.N are connected to sense timing control circuits 47.sub.0 -47.sub.N, respectively. Sense timing control circuits 47.sub.0 -47.sub.N are substantially similar to sense timing control circuits 17.sub.0 -17.sub.N (FIG. 1), except that sense timing circuits 47.sub.0 -47.sub.N are selectively activated by the signal propagated by mock wordlines 44.sub.0 -44.sub.N, respectively.
Through the operation of NAND gates 46.sub.0 -46.sub.N in response to the sense enable signals and row enable signal RE, the appropriate mock wordline is selected to activate the appropriate sense amplifier bank. For example, in a typical folded or segmented bitline architecture, when a wordline near the right side on array block 11.sub.0 is activated in a memory access operation, sense enable signal SE.sub.1 is typically asserted by conventional address decode circuitry (not shown) so as to activate sense amplifier bank 12.sub.1. As a result, mock wordline 44.sub.1 is selected by NAND gate 46.sub.1 and inverting wordline driver 42.sub.1, in response to signal SE.sub.1 and the row enable signal RE. The signal propagated by the activated mock wordline then activates sense timing control circuit 47.sub.1. Because the selected mock wordline is relatively close to the activated normal wordline, the timing in activating the appropriate sense amplifier bank is more accurate compared to the previously described conventional methods.
However, this method still has problems in that activating the sense amplifier banks on either end of the array blocks (i.e., sense amplifier banks 12.sub.0 and 12.sub.N+1) may undesirably cause a mock wordline within the activated array block to be activated. For example, when a wordline near the right side of array block 11.sub.N is activated in a memory access operation, sense enable signal SE.sub.N+1 is typically asserted so as to activate sense amplifier bank 12.sub.N+1. However, in this example architecture, mock wordline 44.sub.N is used to enable sense timing control circuit 47.sub.N+1 to activate sense amplifier bank 12.sub.N+1. Consequently, the activated mock wordline (i.e., wordline 44.sub.N) is undesirably in the activated array block (i.e., array block 11.sub.N). As a result, the activated mock wordline may disturb and/or reduce the voltage differential between the selected bitlines by accessing a row of boundary memory cells simultaneously with the accessing of a row of memory cells by the activated normal wordline. The simultaneous accessing of two rows of memory cells in array block 11.sub.N can result in sense margin reduction or data corruption in array block 11.sub.N. This type of problem also occurs when a wordline near the left side of array block 11.sub.0 is activated in a memory access operation.
Accordingly, there is a need for a timing scheme that accurately tracks the propagation delay in developing data on a bitline during a memory access operation without accessing other memory cells in the activated array block.